Wide Bandgap Semiconductor Advanced Packaging Technology Industry Chain Technical Seminar & Industry Summit Forum
2026.03.26
| Meeting Room E4-M27
Guest
Yu Hongyu
Dean
Prof. Hongyu Yu is head of the Establishment of the College of Integrated Circuits, Shenzhen Polytechnic University, and a professor. Prof. Yu's primary research focuses on integrated circuit technology and devices, including CMOS, novel ultra-high-density memory, GaN devices (GaN HEMTs) and system integration, and electronic ceramics. He has published nearly 450 academic papers, with over 10,500 citations and an H-index of 54. Prof. Yu has also edited 6 books and book chapters and has been granted nearly 34 U.S./European patents and over 100 domestic patents in China. Prof. Yu is the founder of the School of Microelectronics at SUSTech (the national exemplary school of microelectronics), MOE Engineering Research Center for Future Communication Integrated Circuits, Guangdong GaN Device Engineering Technology Research Center, Guangdong Provincial Engineering Research Center Of 3-D Integration (Guangdong 3-D lab) and Shenzhen Key Laboratory of The Third Generation Semiconductor. Prof. Yu was consecutively selected for the list of the World's top 2% most scientists for career-long scientific contributions. He is also an expert in the National high - level talent special support plan, a leading talent in technological innovation in Guangdong Province, and has received the Shenzhen Government's Special Allowance. Prof. Yu is a Fellow of the Institution of Engineering and Technology (IET).
Time & Topic
Thursday, March 26, 2026 10:05 AM - 10:20 AM
Relying on the School of Integrated Circuits / Research Institute for Advanced Intelligent Manufacturing and Application of Integrated Circuits, the School will build an integrated circuit intelligent manufacturing platform and a domestic chip application platform, and establish a Glass Substrate Research Center, 3D Integration Research Center and Characteristic Semiconductor Research Center, focusing on four key directions: AI, general health, low-altitude technology and embodied robots, so as to build a highland for industry-education integration integrating talent training, technology R&D and industrial services. Adhering to the orientation of “manufacturing-oriented and design-supplemented”, the integrated circuit major takes the complete industrial chain platform of integrated circuits as the carrier, focuses on advanced technical fields urgently needing breakthroughs such as characteristic semiconductor manufacturing, 3D integration and glass substrates, and builds a whole-chain talent training model for chip manufacturing and application. Based on the localization demand of the integrated circuit industrial chain, the electronics and communication majors deeply integrate domestic materials, equipment and software application technologies into the talent training system, and strive to build a domestic chip application ecosystem. The School will target the most urgent talent needs of the industry and establish a fully linked industry-education integration platform and supporting professional teaching system. In the future, the School will focus on serving key industrial chains such as AI+, Robotics+, Low-altitude Technology+ and Medical Devices+ in Shenzhen’s “20+8” industrial clusters, and continuously cultivate and supply high-end skilled talents.
Guest
Liu Guoyou
Zhuzhou CRRC Times Semiconductor Co., Ltd., CRRC Scientist
Liu Guoyou, Ph.D., is a senior engineer and a scientist at CRRC. He serves as the deputy director of the National Key Laboratory of Power Semiconductor and Integrated Technology, the vice dean of the School of Integrated Circuit Science and Engineering (CRRC Times Microelectronics College) at Southwest Jiaotong University, and a fellow of the China Electronics Society, the China Electrotechnical Society, and IET. He was selected as a leading talent in the national "Ten Thousand Talents Program" for scientific and technological innovation, an expert with the State Council Special Allowance, and has been awarded the "Guangzhao Science and Technology Award," "Outstanding Engineer Award," and "National Innovation and Excellence Award." He holds positions as a member of the Technical Committee of the National Wide Bandgap Semiconductor Engineering Research Center, a member of the National Semiconductor Device Standard Technical Committee, and the chairman of the Semi-China Compound Semiconductor Standard Technical Committee. He has led over 10 major scientific research and industrialization projects in the field of national power semiconductors. As the first author, he received the National Technology Invention Second Prize, and as a key contributor, he was awarded the National Science and Technology Progress Second Prize and the China Patent Award Silver Prize. He has also won 10 provincial/ministerial-level special prizes or first prizes for science and technology. He has published over 140 papers and obtained more than 150 invention patents, including 7 PCT patents. His work has made pioneering contributions to the systematic breakthrough and industrialization of China's high-power semiconductor technology.
Time & Topic
Thursday, March 26, 2026 10:20 AM - 10:40 AM
Power semiconductor technology is undergoing a profound transformation from single-device innovation to integrated innovation encompassing chips, packaging, and systems. To meet the stringent demands of artificial intelligence and electric vehicles for high efficiency, power density, and reliability, technological advancements are focusing on "precision" design. At the chip level, Si-IGBTs continue to optimize through micro-trenching and backside refinement; SiC-MOSFETs enhance performance via trench gates and copper metallization; while GaN HEMTs address reliability challenges like dynamic resistance. Packaging has become critical for system performance, utilizing low-inductance interconnect technologies such as copper sintering, flexible busbars, and embedded packaging, combined with dual-sided heat dissipation, to create a high-resistance, low-inductance electrical environment that meets the high-speed switching requirements of wide-bandgap devices. In the future, collaborative chip-packaging design, heterogeneous integration, and extreme power solutions for AI power supply will become the core drivers of industry development.
Guest
ZHANG Hao
Senior Chief Engineer, Module R&D Center, BASiC Semiconductor Co., Ltd.
Dr. Zhang Hao is a Senior Chief Engineer at the Module R&D Center of BASiC Semiconductor Co., Ltd. (Shenzhen). He is a recipient of the National Young Talent "Qiming Plan," a core member of the Guangdong Province "Pearl River Talent Plan" Innovation and Entrepreneurship Team, a Guangdong Province "Pearl River Talent Plan" Young Top-Notch Talent, and a Shenzhen Pingshan District "Julong Plan" Leading Talent.Dr. Zhang Hao received his B.S. in Materials Science and Engineering from Central South University in 2008, his Master degree from the Electronic Interconnect Materials Research Division at the Institute of Metal Research, Chinese Academy of Sciences in 2012, and his Doctor of Engineering degree from Osaka University, Japan, in 2016. Prior to joining BASiC Semiconductor Co., Ltd., he held core R&D and marketing positions at Osaka University and Daicel Corporation in Japan. His primary research focus is on the fabrication and application of high-temperature packaging materials for power semiconductors. He has published multiple papers in internationally renowned journals and conferences, and holds more than ten patents in the field of power semiconductor materials and applications.
Time & Topic
Thursday, March 26, 2026 10:40 AM - 11:00 AM
TBD
Guest
Zhengtianye (Daniel) Wang
Prismark Partners, Consultant
Dr. Zhengtianye Wang joined Prismark Partners LLC in 2022. He does business strategy and market analysis of semiconductor and packaging industry, especially focused on business opportunities and technology developement of advanced packaging. He also follows electronic system, semiconductor equipment, networking and AI infrastructure development.
Time & Topic
Thursday, March 26, 2026 11:00 AM - 11:20 AM
Embedded-die-in-PCB technology represents a form of system-level advanced packaging in which the PCB itself becomes part of the power package, integrating bare power semiconductor dies directly into the laminate. By collapsing commutation and gate-drive loops and replacing discrete-package interconnects with short, wide copper structures, this approach fundamentally reduces parasitic inductance and resistance, enabling lower switching and conduction losses, reduced EMI, and improved thermal paths. For automotive power electronics—such as traction inverters and OBC/DC-DC converters—these effects translate into higher efficiency, increased power density, and reduced cooling burden, with early validation already demonstrated in high-performance applications. In AI servers and data centers, where overall energy efficiency is increasingly dominated by power distribution losses and PDN impedance rather than silicon limits alone, embedded die supports tighter point-of-load integration and lower-loss power paths, aligning naturally with the transition to 48 V architectures and rising compute power density.
Guest
Dr. Sandra Engle
VDMA, Head of Sector Group Productronics
Before joining VDMA in 2020, Dr. Engle spent more than 15 years in the printed circuit board and electronics manufacturing industry in Germany and in the United States with leading companies like Sanmina SCI and Mektec. Her experience covers global new business development, new product design, prototype production, product management as well as new market entry strategies. In her current role with VDMA, Dr. Engle represents the interests of the electronics and semiconductor equipment manufacturers towards policy makers, the press and the public. She informs member companies about technology trends and the business climate and organizes international networking events with important potential industry partners. Dr. Engle holds a PhD in organic chemistry with a focus on LCD-technology.
Time & Topic
Thursday, March 26, 2026 11:20 AM - 11:40 AM
The presentation will focus on the relevance of Chiplets as an emerging technology for the European Machinery and Equipment Industry. It will also cover technolgy trends in electronics production, i.e. power electronics.
Guest
Kiko Chen
Macdermid Alpha, Business Development Manager
Kiko Chen is a Business Development Manager at Macdermidalpha, holding a Master’s degree in Brand Marketing. With over 10 years of experience in sales and business development, she currently focuses on the semiconductor advanced packaging field and is committed to promoting comprehensive solutions of ALPHA solder paste flux for advanced packaging technologies including 2.5D, 3D, Fan-out, and SiP.
Time & Topic
Thursday, March 26, 2026 11:40 AM - 12:00 PM
Faced with the trend of miniaturization and high integration in advanced packaging, soldering materials face significant challenges. This speech uses ALPHA solder paste flux as a starting point, highlighting its core benefits of low voiding and high precision, along with customized solutions used in Chiplet and BGA packaging. The goal is to provide insights and references for improving packaging reliability and speeding up the mass production of related technologies.
Guest
Qianfa Liu
Shengyi Technology Co.，LTD., Director of the National Electronic Circuit Substrate Engineering Technology Research Center
Qianfa Liu，Director of the National Electronic Circuit Substrate Engineering Technology Research Center，Senior engineer
Time & Topic
Thursday, March 26, 2026 2:00 PM - 2:20 PM
As third-generation semiconductor (SiC/GaN) devices evolve toward larger sizes and higher power densities, packaging materials face dual challenges in heat dissipation and process reliability. Traditional epoxy fiberglass prepreg (PP) materials are constrained by their structure, typically exhibiting thermal conductivity below 2 W/mK and insufficient flowability, which struggle to meet the interface filling requirements of large chips. This presentation will focus on Sytech's one-stop material solution developed for power applications. Combined with practical application cases, we will elaborate on how this film-based solution, through its outstanding thermal performance and process compatibility, helps customers enhance the power density, reliability, and service life of power modules, thereby providing a solid material foundation for the development of next-generation power electronics.
Guest
Steve JIN
OIP Technology, CEO
25 years expericence in advanced packaging. CEO of OIP technology, used to work in MNC such as Apple and Stmicro. 50 over patents.
Time & Topic
Thursday, March 26, 2026 2:20 PM - 2:40 PM
Aiming on high power package by using panel PLP to improve thermal performance and 3D packaging to integrate controller.
Guest
He Fengguang
Hefei Sineva Intelligent Machine Co.,Ltd, VCTO
VCTO and president of the Central Research Institute of Hefei Sineva . He is an expert in high-speed and high-precision motion control. He led the development of the world's first 10.5G glass substrate clean transfer robot，and also presided over the research and development of large-sized Mini-LED high-volume transfer equipment, achieving the world's first launch of such equipment. Furthermore, he spearheaded the research and development of series semiconductor die bonding machine, successfully launching multiple equipment with a maximum accuracy of 1.5μm.
Time & Topic
Thursday, March 26, 2026 2:40 PM - 3:00 PM
In response to the urgent need for miniaturization and high-density interconnection in advanced packaging (such as Chiplets, 2.5D/3D), Hefei Sineva has started developing a series of semiconductor picking&placing die attaching equipment to achieve independent controllability of high-end semiconductor packaging equipment in China. By integrating precision machinery, real-time control, intelligent vision, and advanced force control technology, Hefei Sineva has successfully solved the core contradiction between "speed" and "accuracy" in advanced packaging, and launched various advanced semiconductor picking&placing equipment to help China's semiconductor packaging technology reach the international advanced level.
Guest
M. Juergen Wolf
An independent consultant and expert in microelectronic packaging technologies
M. Juergen Wolf received the M.S. degree in Electrical Engineering from the Technical University of Chemnitz, Germany. He served as Head of the Department of Wafer Level System Integration at Fraunhofer IZM and as Managing and Scientific Director of Fraunhofer IZM-ASSID in Dresden. He currently works as an independent consultant and expert in microelectronic packaging technologies. His professional activities focus on microelectronic packaging, wafer-level system integration, and 3D integration. Mr. Wolf has authored and co-authored numerous scientific publications and holds several patents in these fields. He currently works as an independent consultant and expert in microelectronic packaging technologies.
Time & Topic
Thursday, March 26, 2026 3:00 PM - 3:20 PM
Since the invention of the transistor, microelectronics has been driven for decades by the continuous downscaling of transistor dimensions and the corresponding increase in integration density — a trend known as Moore’s Law.
Today, microelectronic packaging is undergoing a paradigm shift: from single-component technologies toward complex system-integration approaches that combine multiple components and technology nodes.
The Heterogeneous Integration Roadmap (HIR) defines heterogeneous integration as the integration of separately manufactured components into a higher-level assembly that, as a package, provides enhanced functionality and improved operating characteristics.
Beyond increased functionality, the main significance of heterogeneous system integration lies in meeting market demands for shorter development cycles and reduced costs in emerging application areas such as High-Performance Computing (HPC), Artificial Intelligence (AI), the Internet of Things (IoT), Cyber-Physical Systems (CPS), and Robotics.
Current system-integration technologies are driven by new System-in-Package (SiP) architectures. Innovative technologies are emerging to meet requirements for enhanced performance and miniaturization, high-speed data processing and transmission, efficient power delivery and management, and multi-device integration.
In this context, SiP technologies are the key enablers of today’s heterogeneous system integration — both at the board/substrate level and at the wafer level. All technologies must deliver cost-efficient packaging and system-integration solutions that meet application-specific requirements while ensuring a short time-to-market.
In addition to new integration approaches, process developments, and the adoption of advanced materials, heterogeneous integration requires a holistic approach encompassing design, technology, and reliability considerations.
This talk will focus on key processes for the realization of Heterogeneous System-in-Package solutions.
Guest
Ye Lezhi
Director, Institute of Advanced Semiconductor Equipment, Beijing University of Technology
Lezhi Ye, Ph.D., is an Associate Professor at Beijing University of Technology, Deputy Secretary-General of the China Electronics Special Equipment Industry Association, and Director of the Institute of Advanced Semiconductor Equipment at Beijing University of Technology. He is a recipient of the Beijing Science and Technology Nova Program and has over ten years of R&D experience in semiconductor equipment. He has received five provincial and ministerial-level science and technology awards and has led more than ten research projects, including the National Science and Technology Major Project (02 Special Project), the National Natural Science Foundation of China, and the Beijing Science and Technology Nova Program. He has published one monograph, authored over 30 papers, and holds more than 50 patents.
Time & Topic
Thursday, March 26, 2026 3:20 PM - 3:40 PM
To address defects like voids and cracks in SiC power device packaging, this paper introduces the principles, applications, and advantages of ultrasonic non-destructive testing (NDT), with a focus on key technologies for multi-layer defect imaging in C-scan and T-scan ultrasonic testing. It also details the localization progress of semi-automatic and fully automatic IGBT and copper-clad ceramic board testing systems, which will comprehensively resolve performance and efficiency bottlenecks in the power device inspection industry.
1. Principles of Ultrasonic Non-Destructive Testing
2. Ultrasonic Testing Technology
3. Localization of Fully Automated Ultrasonic Scanning Equipment
Guest
Liu Guanghui
Shenzhen Therlicon Technology Co., Ltd., R&D director
The company's chief R&D officer brings over 20 years of expertise in thermal engineering, thermal equipment development, application, and management. Achieved multiple key technological breakthroughs in the semiconductor thermal equipment industry, advancing equipment localization projects from product planning to market launch; led nearly 100 new product R&D and delivery initiatives, holding multiple invention patents, and is recognized as a highly skilled technical professional with practical expertise.
Time & Topic
Thursday, March 26, 2026 3:40 PM - 4:00 PM
TBD
Guest
Chen Jianyun
Shenzhen Kaiyi Technology Co., Ltd., Senior Manager of PLP Solutions
As a board-level packaging (PLP) and PCB embedding technology specialist at Kaiyi Technology, I have over 20 years of hands-on experience in PCB and semiconductor manufacturing, with extensive expertise in PCB embedding processes.
Time & Topic
Thursday, March 26, 2026 4:00 PM - 4:20 PM
The report, grounded in embedded technology, examines the embedded process for automotive power modules. It details current research and applications in key technologies, demonstrating PCB manufacturers' technical readiness and support for sustainable energy vehicles. Furthermore, by analyzing critical embedded technologies, it offers insights for PCB manufacturers to guide their technological development, particularly in enhancing process capabilities.
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