TGV Advanced Materials and Packaging Industrialization Opportunities Summit Forum
Introduction:
With the increasing complexity of semiconductor circuits, plastic substrates are nearing their capacity limit, particularly with the challenge of rough surfaces negatively impacting the inherent performance of ultra-fine circuits. Consequently, the semiconductor industry seeks a novel substrate solution. Intel anticipates that by the end of the 2020s (2020-2030), the semiconductor manufacturing process may confront constraints in reducing transistor sizes on organic material substrates, introducing mechanical issues such as power consumption, substrate shrinkage, and warping. Therefore, the shift towards glass panels emerges as a crucial factor in the forthcoming semiconductor manufacturing landscape. Intel envisions the launch of a comprehensive glass substrate solution in the latter half of the 2020s, poised to sustain Moore's Law beyond 2030.
This forum will delve into the practical applications of glass-based chip board across various domains, including Mini/Micro direct display, MIP packaging, 2.5D/3D packaging, radio frequency chip carrier boards, optical communication chip carrier boards, and other chip carrier boards, particularly advanced semiconductor packaging.
Previous Speech Companies:
Topics:
- Opportunities and challenges for TGV technology under the Al+Chiplet trend
- Solutions of glass material manufacturers in glass substrate applications
- Development of advanced packaging technology and its material requirements
Participation Consulting:
Sinsia Xing
Project Director
Tel.:+86 21 2020-5553
E-mail:sinsia.xing@mm-sh.com
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TGV Advanced Materials and Packaging Industrialization Opportunities Summit Forum
Host: Tingyu Lin Guangdong Fozhixin Microelectronics Technology Research Co., Ltd. Chief Scientist
Time | Topic | Guest |
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Time | TopicHost's Opening Speech | Guest |
Time | TopicLeader's Speech |
Guest
Xiekang Yu |
Time | TopicMarket Opportunities and Challenges for Advanced Packaging with Glass Material |
Guest
Zhengtianye (Daniel) Wang |
Time | TopicHigh-Density Glass-Based FCBGA Packaging Substrate |
Guest
Chengqiang Cui |
Time | TopicTea break & socializing | Guest |
Time | TopicSCHOTT's Glass Solutions Enable Advanced Semiconductor Packaging |
Guest
Guangjun Zhang |
Time | TopicGlass Core Substrates: A New Generation of Advanced Packaging Technology |
Guest
Jiamiao Tang |
Time | TopicJodell Robotics Ingenuity to Create Semiconductor Packaging Solutions |
Guest
Wilford Zhou |
Time | TopicTBC |
Guest
Mystery Guest |
Time | TopicAdvancements, Applications, and Challenges in Advanced Through Glass Via (TGV) Technology Research |
Guest
Daquan Yu |
Time | TopicTea break & networking | Guest |
Time | TopicRoundtable Discussion | Guest |
Time | TopicThe Development of IPC-6921 IC Packaging Substrate Standards |
Guest
Gang Liu |
Time | TopicHigh Density Panel Level Technology Enabling Advanced Packaging |
Guest
David Fang |
Time | TopicAdvanced Packaging Materials for High Computing Power and High Power Environments |
Guest
Song Jing |
Time | TopicThe Application of Glass Substrates In High Computing AI Chips |
Guest
Song Jin |
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Xiekang Yu
Vice Chairman | National Integrated Circuit
Leader's Speech
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Zhengtianye (Daniel) Wang
Prismark Partners | Consultant
Dr. Zhengtianye Wang joined Prismark Partners LLC in 2022. He obtained his B.Sc. degree in Material Physics in 2017 from University of Science and Technology of China and his Ph.D. in Material Science and Engineering in 2022 from University of Delaware. He does business strategy and market analysis of semiconductor and packaging industry, especially focused on business opportunities and technology developement of advanced packaging. He also follows electronic system, semiconductor equipment, networking and AI infrastructure development.
Market Opportunities and Challenges for Advanced Packaging with Glass Material
To enable higher interconnect density and power efficiency in a large form factor pacakge assembly and development of co-pacakged optics, a glass layer is proposed to replace the organic core of a FCBGA substrate and/or the silicon interposer. Glass is rigid, stable, low dielectric loss and enabling high through hole density, which is essential for complex devices for HPC applications. Intel's commitment to integrate glass technology has fueled intensive investment and R&D in the supply chain. This paper will address the market opportunities and technology challenges of glass substrates, in the hope of supporting the industry to prepare for such a technology transition.
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Chengqiang Cui
Guangdong Fozhixin Microelectronics Technology Research Co., Ltd. | Chairman
High-Density Glass-Based FCBGA Packaging Substrate
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Guangjun Zhang
SCHOTT Group. | Senior Manager, Global Product Management
He graduated from Shanghai Institute of optical and fine mechanics, Chinese Academy of sciences. Now he is the senior manager of Thin Glass and Wafer Business Unit in SCHOTT Group, responsible for product management and business development of SCHOTT Specialty Glass in the fields of imaging, sensing and semiconductors.
SCHOTT's Glass Solutions Enable Advanced Semiconductor Packaging
SCHOTT is taking steps to support the integrated circuit (IC) industry in advancing the pace of Moore's Law with new materials. This development is needed for more powerful computing intended for applications such as artificial intelligence (AI). As uncompromised, high-quality glass substrates are crucial for enabling advanced packaging in the upcoming decade, SCHOTT is proactively setting the course to enable the industry to innovate even further. The audience's take aways will be on current SCHOTT offerings and future developments with respect to glass based IC Substrates/ Interposers as well on Carrier Wafers.
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Jiamiao Tang
AKM Meadville Electronics (Xiamen) Co., Ltd. | General Manager of FCBGA
Long-term work in multinational companies and engage in ABF high-end substrate research and development, factory construction and large-scale production.With over twenty years of experience in the field of high-density ABF substrate for computer CPU chips, server chips, EMIB, glass and ceramic related to high-computing chips. Worked at IBM substrate factory in Japan(now Kyocera Yasu Plant) from 2001 to 2003; Joined Intel in July 2003, focusing on high-end ABF substrate technology development; Worked in the United States from 2009 to 2010, assisting in the establishment and production of top international ABF substrate factories; From 2018 to 2022, served as the key technical and operational leader of Intel's global board business unit (Chair of the Technical Committee, Chair of the Innovation Committee, Chair of the PCS Smart Control Committee, and Chairman of the Global Packaging Material Change Control Committee). In the past six years, he led the establishment of two intelligent factories dedicated to ABF substrate for Intel, guiding the company growing out of nothing, and being a leading factory in the global industry from weak in technology.Received the Intel Global Technology and Manufacturing Achievement Award. Granted 18 international patents and more than 20 articles and 4 Intel trade secrets.
Glass Core Substrates: A New Generation of Advanced Packaging Technology
The glass base ABF substrate uses silicon base glass as the core substrate, which solves the industry pain point of organic substrate warping.The advantages of glass-based ABF substrate are significant, with minimal expansion and contraction deformation at high temperatures, reducing graphic distortion by 50%, and providing the dimensional stability required for tight layer-to-layer direct stacking interconnections.The interconnection density of glass substrate can be increased by up to 10 times; the mechanical performance of glass substrate is improved, enabling the realization of large-size, high-assembly-yield external packaging. Glass substrate provides greater flexibility in design rules for power transmission and signal routing. It can seamlessly integrate with optical components and embed sensors and capacitors into glass substrate at higher temperature processes, offering better power transmission solutions.Due to the above advantages of glass substrate, it is very suitable for chiplet application scenarios of high density and high computing power, and can meet the needs of chiplet high computing power chip.As a leading domestic company in the field of package substrate, AKMMV has conducted in-depth research on glass-based ABF substrate technology, contributing to the development and ecological chain construction of glass-based ABF carrier board technology by promoting cluster development, chain development, and collaborative development.
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Daquan Yu
Xiamen Sky Semiconductor Technology Co., Ltd. | Chairman
Dr. Daquan Yu is a Distinguished Professor of Xiamen University and the founder of Xiamen Sky Semiconductor technology Co., Ltd.,and graduated from Dalian University of Technology on 2004.He was the President of Research Academy of Advanced Packaging Technology of TSHT Group from 2014 to 2019. Before that, he was a professor of Institute of Microelectronics, Chinese Academy of Sciences from 2010 to 2015. He had carried out research work at Fraunhofer IZM in Germany, and Institute of Microelectronics in Singapore from 2005 to 2010. He has authored or co-authored more than 200 peer-reviewed technical publications and holds more than 100 patents.
Advancements, Applications, and Challenges in Advanced Through Glass Via (TGV) Technology Research
The fast growth of Intelligent Mobile Terminal, IoT, 5G, AI brings more critical requirements for advanced packaging. Glass is an ideal substrate for semiconductor devices. The key challenges are via formation, via filling and process integration. With the development of LIDE, low cost via formation and filling becomes the key issues. The main applications for TGVs are microfluidics, IPD, MEMS packaging, fan-out, 2.5D interposer as well as Photonic Packaging. The progress of these applications is presented and the challenges are summarized.
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Wilford Zhou
Jodell Robotics | Industry Director
Wilford Zhou, graduated from Harbin Institute of Technology with a master's degree in mechanical manufacturing, served as the industry director of Jodell Robotics, responsible for Jodell industry development strategy and industry expansion, has more than 10 years of experience in foreign companies, and has served as Lenze, NORD national industry sales director.
Jodell Robotics Ingenuity to Create Semiconductor Packaging Solutions
1. Introduction of Jodell Robotics Company
2. The solution of Jodell Robotics in the field of semiconductor packaging
3. Advantages of Jodell Robotics products -
Gang Liu
Guangzhou Guangxin Packaging Substrate Co., Ltd | Quality Director of Packaging Substrate Division
IPC-6921 Committee Chair;
Lean six sigma Master Black Belt;
QC Senior Diagnostician of Shenzhen Quality Association;
Shennan Circuit Process Quality Expert, Intelligent Manufacturing Expert;The Development of IPC-6921 IC Packaging Substrate Standards
• Introduction to IPC-6921 standard chairman unit GreaTech Substrates
• Introduction to the IPC-6921 standard development task group and development background
• IPC-6921 IC substrate standard basic structure
• Presentation form of standard content related to appearance acceptance and reliability of IC Substrate. -
David Fang
ECHINT Technology Co., Ltd. | VP&CTO
David Fang now work in ECHINT Technology as VP & CTO. He has more than 32 years working experience in chip design, semiconductor process, chip packaging & testing areas. He used to work as VP and CTO in Powertech Technology for 22 years, established R&D center. Besides, he led R&D team in developing advanced packaging technology such as ultra thin chips stacking, fine-pitch bumping, WLCSP, FOPLP, CISCSP, 3DIC, and 2.5D, and introduced into mass production during his tenure. In addition, David Fang has granted 55 patents worldwide.
High Density Panel Level Technology Enabling Advanced Packaging
In recent years, AI/HPC and ADAS have driven the development of semiconductors. As Moore's Law slows down, heterogeneous integration of chiplet has become an important aspect of future semiconductor development. Echint Technology develops high-density panel level fan-out packaging technology, which is combined with high-density multi-layer substrate to form an advanced heterogeneous integrated package. However, as the functions and performance of chips become more powerful, the complexity of heterogeneous integration becomes higher, and the area of packaging and substrate becomes larger. The packaging yield and quality are challenged, and the cost also increases significantly. Echint Technology tries to use high-density panel-level packaging technology, glass carrier technology, high-density RDL and other technologies to develop advanced packaging to improve the performance and reliability of heterogeneous integration packging.
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Qianfa Liu
Guangdong SYTECH Technology Co., Ltd. | Director of the National Electronic Circuit Substrate Engineering Technology Research Center
Advanced Packaging Materials for High Computing Power and High Power Environments
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Song Jin
Shanghai BIREN Technology Co, Ltd. | Packaging Process Specialist
Graduated from Zhejiang University, Bachelor of Chemical Engineering and technology, responsible for packaging new product engineering introduction and mass production maintenance. Prior to joining Biren, Jing worked in ASE, Samsung SDI, Huawei Technologies and other companies in charge of packaging substrate process, packaging process, packaging materials verification and import, and have nearly 10 years of work experience in chip packaging and substrate industry.
The Application of Glass Substrates In High Computing AI Chips
The analysis of AI chip development challenges, AI chip technical difficulties, combined with the current American choke policy, it is concluded that Chiplet "multi-chip closing technology" will become the only way to improve the performance of a single package.
The development of large-size chips, we must solve the problem of substrate warping, glass substrate has excellent mechanical properties, physical properties and optical characteristics, so as to better expand the assembly of small chip complex in the large-size package of multi-chip interconnection, to provide chip design architects with more design space.